1. Field of the Invention
The disclosed embodiments of the present invention relate to testing semiconductor products, and more particularly, to an apparatus and method for applying an at-speed functional test with a lower-speed tester.
2. Description of the Prior Art
Scan chain is a technique used in a circuit design for scan test. More specifically, the scan chain provides a simple way to set and observe every flip-flop in a circuit design. A clock signal controls all of the flip-flops in the scan chain during a shift phase and a capture phase. Hence, a test pattern can be entered into the scan chain composed of flip-flops, and the state of every flip-flop can be read out to determine if the circuit design passes the scan test.
Growing gate counts and increasing timing defects with small fabrication technologies force improvements in test quality to maintain the quality level of chips delivered to customers after testing. Therefore, the scan chain based at-speed test may be used to maintain test quality for larger, more complex chips made using advanced fabrication processes. To realize the scan chain based at-speed test, a high-speed tester is required to feed the test pattern at a high clock rate to run the scan test on a device under test with a scan chain operating under the high clock rate. However, using the high-speed tester would increase the test cost inevitably.